Electric Stress-Induced Threshold Voltage Instability of Multi-Layer MoS2 Field Effect Transistors

본 논문에서는 전이금속 칼코겐화합물(transition-metal dichalcogenide) 이황화몰리브덴(MoS2)으로 이용하여 전계효과 트랜지스터(field effect transistor)를 제작하고, 이 소자의 전기적 구동 특성의 안정성에 대해서 연구를 하였다. 소자에 걸어주는 게이트 전압의 다양한 stress 환경(가령, 전압의 polarity, sweep 속도, stress를 가하는 시간, 측정 환경 등)에서 MoS2 트랜지스터 소자의 문턱전압(threshold voltage)의 안정성/불안정성에 대한 기초적인 연구 결과이다.

Abstract: We investigated the gate bias stress effects of multi-layered MoS2 field effect transistors (FETs) with a back-gated configuration. The electrical stability of the MoS2 FETs can be significantly influenced by the electrical stress type, relative sweep rate, and stress time in an ambient environment. Specifically, when a positive gate bias stress was applied to the MoS2 FET, the current of the device decreased and its threshold shifted in the positive gate bias direction. In contrast, with a negative gate bias stress, the current of the device increased and the threshold shifted in the negative gate bias direction. The gate bias stress effects were enhanced when a gate bias was applied for a longer time or when a slower sweep rate was used. These phenomena can be explained by the charge trapping due to the adsorption or desorption of oxygen and/or water on the MoS2 surface with a positive or negative gate bias, respectively, under an ambient environment. This study will be helpful in understanding the electrical-stress-induced instability of the MoS2-based electronic devices and will also give insight into the design of desirable devices for electronics applications.

Authors: Kyungjune Cho(서울대), Woanseo Park(서울대), Juhun Park(서울대), Hyunhak Jeong(서울대), Jingon Jang(서울대), Tae-Young Kim(서울대), Woong-Ki Hong(KBSI)*, Seunghun Hong(서울대), Takhee Lee(서울대)*

ACS Nano, Just Accepted Manuscript
DOI: 10.1021/nn402348r
Publication Date (Web): August 8, 2013